1. Field of the Invention
The present invention relates to a semiconductor device including a circuit comprising a thin film transistor (hereinafter referred to as a TFT) over a substrate having an insulating surface and a method of fabricating the same. Particularly, the invention relates to a structure of an electro-optical device typified by a liquid crystal display device, and an electronic equipment incorporating the electro-optical device, or relates to a structure of an electro-optical device typified by an EL (electro luminescence) display device using an EL material capable of obtaining electro luminescence, and an electronic equipment incorporating the electro-optical device.
Incidentally, in the present specification, the term xe2x80x9csemiconductor devicexe2x80x9d indicates any devices functioning by using semiconductor characteristics, and includes the foregoing electro-optical device and the electronic equipment incorporating the electro-optical device in its category.
2. Description of the Related Art
A semiconductor device including a large area integrated circuit made of TFTs is under development. An active matrix type liquid crystal display device, an EL display device, and a contact type image sensor are its typical examples.
The TFT can be classified according to its structure and fabricating method. Particularly, since a TFT (crystalline TFT) including a semiconductor film having crystal structure as an active layer has a high field effect mobility, it has been possible to form various functional circuits.
In the present specification, the semiconductor film having the crystal structure includes a single crystal semiconductor, a polycrystal semiconductor, and a microcrystal semiconductor, and further, includes a semiconductor disclosed in Japanese Patent Application Laid-open No. Hei. 7-130652, No. Hei. 8-78329, No. Hei. 10-135468, No. Hei. 10-247735, or No. Hei. 10-135469. The disclosure of the above Japanese Patent Applications is incorporated with herein by reference.
In an active matrix type liquid crystal display device, for every functional block, a pixel region (also called a pixel matrix circuit) comprising n-channel TFTs and a driver circuit including a CMOS circuit as a basic unit, such as a shift register circuit, a level shifter circuit, a buffer circuit, and a sampling circuit, are formed over one substrate.
In the contact type image sensor, an integrated circuit such as a sample-and-hold circuit, a shift register circuit, and a multiplexer circuit is formed by using TFTs.
Since these circuits do not necessarily have the same operation condition, characteristics required for TFTs have been naturally different not a little from one another.
The characteristics of a field effect transistor such as a TFT can be considered by dividing them into a linear region where a drain current increases in proportion to a drain voltage, a saturation region where even if a drain voltage is increased, a drain current is saturated, and a cut-off region where even if a drain voltage is applied, a current does not flow ideally. In the present specification, the linear region and the saturation region are referred to as an ON region of a TFT, and the cut-off region is referred to as an OFF region. For convenience, a drain current in the ON region is referred to as an ON current, and a current in the OFF region is referred to as an OFF current.
A pixel portion comprises a switching element made of an n-channel TFT (hereinafter referred to as a pixel TFT) and an auxiliary holding capacitance, and applies a voltage to a liquid crystal to drive it. Here, the liquid crystal is required to be driven by an alternating current, and a system called frame inversion driving has been adopted. Thus, as characteristics of TFTs to be required, it has been necessary that the OFF current is sufficiently reduced.
Since a buffer circuit of a driver circuit is applied with a high driving voltage, it has been necessary to increase withstand voltage. Besides, in order to increase current driving performance, it has been necessary to sufficiently secure the ON current.
However, there has been a problem that the OFF current of a crystalline TFT is apt to become high. The crystalline TFT has been regarded as being inferior to a MOS transistor (transistor fabricated on a single crystal semiconductor substrate) used for an LSI or the like in reliability. For example, a deterioration phenomenon such as a lowering of ON current has been sometimes observed in the crystalline TFT. It has been considered that this cause is a hot carrier effect, and hot carriers generated by a high electric field in the vicinity of a drain cause the deterioration phenomenon.
As a structure of a TFT, a low concentration drain (LDD: Lightly Doped Drain) structure has been known. In this structure, an impurity region having a low concentration is provided between a channel forming region and a source region or drain region added with an impurity at a high concentration, and this low concentration impurity region is called an LDD region.
According to positional relation to a gate electrode, the LDD structure includes a GOLD (Gate-drain Overlapped LDD) structure where it overlaps with the gate electrode, an LDD structure where it does not overlap with the gate electrode, and the like. The GOLD structure has been able to relieve a high electric field in the vicinity of a drain, to prevent the hot carrier effect, and to improve the reliability. For example, in xe2x80x9cMutsuko Hatano, Hajime Akimoto and Takeshi Sakai, IDEM 97 TECHNICAL DIGEST, p 523-526, 1997xe2x80x9d, it is ascertained that extremely excellent reliability can be obtained in the GOLD structure of a side wall comprising silicon as compared with TFTs of other structures.
On the other hand, as another problem in relation to a large area integrated circuit, there has been a problem of wiring. An integrated circuit comprising TFTs is provided with a gate wiring line connected to a gate electrode and a data wiring line connected to a source electrode or drain electrode. Particularly, the gate wiring line has a problem of a wiring delay due to influence of parasitic capacitance and wiring resistance. Although a material such as molybdenum (Mo), tantalum (Ta), or tungsten (W) has been used for the gate electrode and the gate wiring line in view of heat resistance, these have a sheet resistivity of about 10 Ù, and have not been suitable for a large area integrated circuit. It has been originally preferable to use a low resistance material such as aluminum (Al) or copper (Cu).
However, the GOLD structure has a problem that the OFF current becomes high as compared with a normal LDD structure, and it has not been necessarily preferable to form all TFTs with the GOLD structure in a large area integrated circuit. For example, in a pixel TFT, if the OFF current is increased, a power consumption is increased and an abnormality appears on image display. Thus, it has not been preferable to apply a crystalline TFT of the GOLD structure as it is.
Moreover, the LDD structure has a problem that the ON current is decreased by an increase of series resistance. Although the ON current can be freely designed through a channel width of a TFT and the like, for example, it has not been always necessary to provide the LDD structure in the TFT constituting a buffer circuit.
The present invention has a problem of providing a TFT with an optimum structure for every functional circuit in a semiconductor device including a large area integrated circuit typified by an active matrix type liquid crystal display device, an EL display device, and an image sensor. Besides, the invention has a problem of providing a method of fabricating such TFTs on the same substrate through the same steps.
Moreover, the invention has a problem of providing a wiring structure in which a reduction in wiring resistance is compatible with an increase in integration in a semiconductor device including a large area integrated circuit typified by an active matrix type liquid crystal display device, an EL display device, and an image sensor.
The present invention relates to a technique to solve such problems, and has an object to realize a crystalline TFT capable of obtaining reliability comparable to or superior to a MOS transistor. Another object of the invention is to increase reliability of a semiconductor device including a large area integrated circuit in which various functional circuits comprise such TFTs.
In order to solve the above problems, the present invention is characterized by making such a structure that an LDD region including a region which overlaps with a gate electrode and a region which does not overlap with the gate electrode is provided in one TFT.
Moreover, in a semiconductor device including a large area integrated circuit typified by an active matrix type liquid crystal display device, an EL display device, and an image sensor, for the purpose of realizing a TFT having an optimum structure for every functional circuit, the present invention makes it possible to differentiate a ratio of a region of an LDD region overlapping with a gate electrode to a region not overlapping with the gate electrode for every TFT.
Moreover, in a semiconductor device including a large area integrated circuit typified by an active matrix type liquid crystal display device, an EL display device, and an image sensor, for the purpose of realizing a gate wiring line effectively using Al or Cu of a low resistance material, such a wiring structure is made that a wiring line of a clad structure is partially formed.
Thus, the structure of the present invention is such that in a semiconductor device including, over a substrate having an insulating surface, a semiconductor layer, a gate insulating film, a gate electrode, and a gate wiring line connected to the gate electrode, the gate electrode comprises a first conductive layer or a first conductive layer and a second conductive layer, and the gate wiring line is constructed by a region comprising the same conductive layer as the gate electrode and a region having a clad structure where a third conductive layer is covered with the first conductive layer and the second conductive layer.
The semiconductor layer includes a channel forming region, a first impurity region of one conductivity type, and a second impurity region of the one conductivity type sandwiched between the channel forming region and the first impurity region of the one conductivity type and being in contact with the channel forming region, and a part of the second impurity region of the one conductivity type overlaps with the gate electrode through the gate insulating film.
The first conductive layer and the second conductive layer applied to the present invention use one kind or plural kinds of elements selected from titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo), or a compound containing the element as its main material. The third conductive layer comprises a low resistance conductive material typified by a kind of or plural kinds of elements selected from aluminum (Al) and copper (Cu), or a compound containing the foregoing element as its main material.
The present invention can be applied to a semiconductor device including a pixel region comprising an n-channel thin film transistor and a CMOS circuit comprising an n-channel thin film transistor and a p-channel thin film transistor.
However, in the foregoing CMOS circuit, it is not always necessary to apply the structure of the present invention to the p-channel TFT.
Moreover, another structure of the present invention is characterized by comprising a step of forming a semiconductor layer over a substrate having an insulating surface, a step of forming a gate insulating film to be in contact with the semiconductor layer, a step of forming a first conductive layer to be in contact with the gate insulating film, a step of forming a second impurity region by selectively adding an impurity element of one conductivity type to the semiconductor layer, a step of forming a third conductive layer to be in contact with the first conductive layer, a step of forming a second conductive layer to be in contact with the first conductive layer and the third conductive layer, a step of forming a gate electrode from the first conductive layer and the second conductive layer, a step of forming a gate wiring line from the first conductive layer, the second conductive layer, and the third conductive layer, a step of forming a first impurity region by selectively adding an impurity element of the one conductivity type to the semiconductor layer, and a step of removing a part of the gate electrode.
Moreover, the structure of the present invention is characterized by comprising a step of forming a semiconductor layer over a substrate having an insulating surface, a step of forming at least a first island-like semiconductor layer and a second island-like semiconductor layer by removing a part of the semiconductor layer, a step of forming a gate insulating film to be in contact with the first island-like semiconductor layer and the second island-like semiconductor layer, a step of forming a first conductive layer to be in contact with the gate insulating film, a step of forming a second impurity region by adding an impurity element of one conductivity type to at least a selected region of the first island-like semiconductor layer, a step of forming a third conductive layer to be in contact with the first conductive layer, a step of forming a second conductive layer to be in contact with the first conductive layer and the third conductive layer, a step of forming a gate electrode from the first conductive layer and the second conductive layer, a step of forming a gate wiring line from the first conductive layer, the second conductive layer, and the third conductive layer, a step of forming a first impurity region by adding an impurity element of the one conductivity type to a selected region of the first island-like semiconductor layer, a step of forming a third impurity region by adding an impurity element of a conductivity type opposite to the one conductivity type to a selected region of the second island-like semiconductor layer, and a step of removing a part of the gate electrode.